Silicon Labs /Series1 /EFR32FG12P /EFR32FG12P431F1024IM48 /LEUART0 /CTRL

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Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AUTOTRI)AUTOTRI 0 (DATABITS)DATABITS 0 (NONE)PARITY 0 (STOPBITS)STOPBITS 0 (INV)INV 0 (ERRSDMA)ERRSDMA 0 (LOOPBK)LOOPBK 0 (SFUBRX)SFUBRX 0 (MPM)MPM 0 (MPAB)MPAB 0 (BIT8DV)BIT8DV 0 (RXDMAWU)RXDMAWU 0 (TXDMAWU)TXDMAWU 0 (NONE)TXDELAY

TXDELAY=NONE, PARITY=NONE

Description

Control Register

Fields

AUTOTRI

Automatic Transmitter Tristate

DATABITS

Data-Bit Mode

PARITY

Parity-Bit Mode

0 (NONE): Parity bits are not used

2 (EVEN): Even parity are used. Parity bits are automatically generated and checked by hardware.

3 (ODD): Odd parity is used. Parity bits are automatically generated and checked by hardware.

STOPBITS

Stop-Bit Mode

INV

Invert Input and Output

ERRSDMA

Clear RX DMA on Error

LOOPBK

Loopback Enable

SFUBRX

Start-Frame UnBlock RX

MPM

Multi-Processor Mode

MPAB

Multi-Processor Address-Bit

BIT8DV

Bit 8 Default Value

RXDMAWU

RX DMA Wakeup

TXDMAWU

TX DMA Wakeup

TXDELAY

TX Delay Transmission

0 (NONE): Frames are transmitted immediately

1 (SINGLE): Transmission of new frames are delayed by a single bit period

2 (DOUBLE): Transmission of new frames are delayed by two bit periods

3 (TRIPLE): Transmission of new frames are delayed by three bit periods

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